Control loops, in the form of frequency or phase lock loops (FLL/PLL), provide frequency adjustable output signals that are kept at a stable nominal frequency through a feedback arrangement. Such control loops are used in a range of telecommunications applications, for example in FM modulators, FM demodulators and frequency synthesisers.
The resolution of the adjustment of these control loops is often limited to relatively large discrete steps. For example, in an integer PLL with a fixed frequency reference signal, and a divider in the feedback path, the output frequency can only be adjusted to a multiple of the reference frequency by adjusting the divider value. Therefore, it is not possible to adjust the output frequency to an arbitrarily fine resolution. To increase the output frequency resolution, it is possible to use a divider that facilitates a larger division ratio in conjunction with a lower reference frequency. One of the drawbacks of this approach is that the smaller the reference frequency, the longer it takes the FLL/PLL to achieve lock.
One solution is to use a reference signal source that has an adjustable output frequency as an input to an integer or fractional N PLL. In this way the reference frequency can be increased by a small amount while coarse frequency adjustment in the integer N PLL is appropriate to achieve a fast phase lock time. The reference frequency source must be finely adjusted for the overall system to acquire frequencies between these coarse frequency steps caused by changing the dividers in the integer or fractional N PLL.